1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to an integrated circuit with an electrostatic discharge protection circuit.
2. Description of the Prior Art
Generally, electrostatic discharge (ESD) stress testing for integrated circuits (ICs) include pin-to-pin testing modes, such as a positive-to-VSS (PS) mode, a negative-to-VSS (NS) mode, a positive-to-VDD (PD) mode and a negative-to-VDD (ND) mode, and a testing mode between power pins, such as a VDD-to-VSS (DS) mode. Take the PS mode for example. A positive ESD stress is applied to an input pin to be tested so as to discharge a VSS pin connected to ground while a VDD pin and other pins are floating.
For complementary metal-oxide semiconductor (CMOS) integrated circuits, components for ESD protection circuits can be diffusion or poly-resistors, diodes with p-n junction, MOS transistors, field-oxide devices, bipolar junction transistors, or SCR devices with p-n-p-n structure. However, these components have different properties and thereby have different ESD protection capabilities.
Please refer to FIG. 1, which is an input ESD protection circuit in an integrated circuit 1 based on the prior art. The IC 1 comprises an input pad (I/P) 16, an input resistor R1, an internal circuit 13, a power clamp circuit 14, and an input ESD protection circuit. The input ESD protection circuit comprises two parasitical resistances R2, R3, an N-type metal oxide semiconductor (MOS) transistor 22 and a PMOS transistor 24, so that ESD protection is formed between the input pad 16 and VDD and between the input pad 16 and VSS. The power clamp circuit 14 is an ESD protection between VDD and VSS.
The input ESD protection circuit of FIG. 1 utilizes a gate-grounded NMOS transistor and a gate-grounded PMOS transistor, generating a protection circuit for two-way protection. It can provide a good performance for ESD protection, but triggering voltages for transistors are significantly high.
Pleaser refer to FIG. 2, which is an input ESD protection circuit in an integrated circuit 2 based on the prior art. The input ESD protection circuit of the IC 2 comprises two diodes 26, 28 so as to form ESD protection between the input pad 16 and VDD and between the input pad 16 and VSS.
For example, since a forward-biased diode has a working voltage (about 0.8 to 1.2 volts) far smaller than that (about −13 to −15 volts) of a reverse-biased diode, heat generated by the forward-biased diode is accordingly far smaller than that of the reverse-biased diode if ESD currents flowing through these two diodes are equal. The forward-biased diode has an ESD protection capability far superior to that of the reverse-biased diode if their sizes are equal. A diode that an ESD protection circuit comprises is usually forward-biased. Therefore, it only provides a one-way ESD protection circuit with lower ESD protection capability than that of FIG. 1.
Please refer to FIG. 3, which is an input ESD protection circuit in an integrated circuit 3 based on the prior art. The input ESD protection circuit of the IC 3 comprises two NMOS transistors 32, 34, and a parasitical substrate resistance Rsub to form the ESD protection circuit.
In FIG. 3, the prior art adopts a substrate-triggered technology to improve the performance of ESD protection. As shown in FIG. 3, the transistor 34 is made to be in the breakdown situation to trigger a body terminal of the transistor 32 to be turned on, so that the ESD current can be bypassed through the transistor 32. However, the drawback is that the triggering voltage of the transistor 34 in the breakdown situation is high.
Please refer to FIG. 4, which is an input ESD protection circuit in an integrated circuit 4 based on the prior art. The input ESD protection circuit of the IC 4 comprises two NMOS transistors 44, 42, a resistor 46, a capacitor 48, and a parasitical substrate resistance Rsub to form the ESD protection circuit.
In FIG. 4, the prior art utilizes the resistor 46 and the capacitor 48 to charge and discharge. As shown in FIG. 4, the transistor 44 is turned on earlier so as to bypass the ESD current. Since the charge/discharge time depends on values of the resistor 46 and the capacitor 48, high loading at the input pad 16 results and performance for high-speed data access is reduced.